Plain-English definitions for semiconductor memory terms used in procurement, supply chain, and product design. From DDR5 to HBM3E, NAND to NOR Flash.
NAND flash cells stacked vertically rather than spread flat on a silicon die. Stacking enables higher storage density without requiring smaller cell geometries, improving yield and cost per GB. Nearly all commercial NAND produced today is 3D NAND.
A surface-mount IC package where the chip connects to the PCB through an array of solder balls on its underside. Most modern memory components (LPDDR5X, eMMC, HBM) use BGA packaging. BGA parts are soldered directly to the board and are not field-replaceable.
Double Data Rate 4 SDRAM. The 4th generation of the DDR standard, introduced in 2014. Runs at 1.2V. The dominant memory type in servers and PCs through the early 2020s. Now in end-of-life planning as DDR5 takes over in new designs.
Double Data Rate 5 SDRAM. The 5th generation of DDR memory, introduced in 2021. Runs at 1.1V and delivers higher bandwidth than DDR4. Standard for Intel 12th Gen+ and AMD Ryzen 7000+ platforms. Not backward-compatible with DDR4 slots.
The dominant form of volatile memory in computing devices. DRAM stores each bit in a capacitor that must be continuously refreshed. It is fast but loses data when power is removed. Types include DDR4, DDR5, LPDDR5X, and HBM.
A soldered-on flash storage standard that combines NAND flash and a controller in a single BGA package. Widely used in IoT devices, industrial controllers, and entry-level smartphones. Not field-replaceable. Typically available in 4 GB to 256 GB capacities.
A manufacturer designation indicating that a component is being discontinued. EOL parts may receive last-time-buy (LTB) notices giving customers a window to place final orders. Planning for EOL transitions is a core function of electronic component procurement.
Graphics DDR6 and its extended variant. High-speed DRAM designed specifically for GPU memory. Used in consumer and workstation graphics cards (NVIDIA RTX series, AMD RX series). Distinct from HBM, which is used in data center AI accelerators.
A type of DRAM that stacks multiple dies vertically using Through-Silicon Via (TSV) technology and connects them to a processor via a silicon interposer. Delivers extremely high memory bandwidth (up to 1.15 TB/s for HBM3E) at lower power than conventional DRAM. Essential for AI training accelerators.
The current generation of High Bandwidth Memory. Offers up to 1.15 TB/s bandwidth per stack and up to 36 GB per stack capacity. Used in NVIDIA H200, B200, AMD MI300X, and Google TPU v5. Supply is critically constrained as of 2026, with 18–24 month lead times.
The elapsed time from placing a purchase order to receiving the component. In memory procurement, lead times vary from 4 weeks (DDR4 from stock) to 24+ months (HBM3E). Planning around lead times is critical to avoiding production line stoppages.
Low Power DDR5 and its extended variant. Optimized for mobile and edge devices, running at 0.5V for best-in-class power efficiency. Used in flagship smartphones, thin laptops, and edge AI modules. Physically incompatible with DDR5 — requires dedicated SoC support. LPDDR5X reaches speeds up to 8533 Mbps.
NAND flash that stores 2 bits per cell. Offers a balance of endurance and density. Largely replaced by TLC in consumer applications; industrial-grade MLC (sometimes called eMLC) persists in enterprise and automotive applications requiring higher write endurance than TLC.
A type of non-volatile storage memory that retains data without power. NAND is organized in 'pages' and 'blocks' and must be erased before being re-written. It is the technology inside SSDs, eMMC modules, UFS chips, and USB flash drives.
A type of non-volatile flash memory optimized for random-access reads rather than sequential storage. Slower to write than NAND but supports execute-in-place (XiP) — code can run directly from NOR without being copied to RAM. Used for firmware storage in embedded systems, automotive ECUs, and IoT devices. Key vendors: Winbond, Macronix.
NAND flash that stores 4 bits per cell. Offers the highest density and lowest cost per GB of any NAND type. Write endurance is lower than TLC, making it best suited for read-heavy workloads such as high-capacity cold storage or video surveillance.
Inventory held above normal operating levels as a buffer against supply disruptions or demand spikes. In memory procurement, safety stock planning is especially important for components with long lead times (LPDDR5X, HBM) or those approaching EOL.
NAND flash that stores 1 bit per cell. The highest endurance and fastest of all NAND types, but also the most expensive and lowest density. Used in industrial, military, and aerospace applications where reliability and write cycles matter more than cost per GB.
Static Random Access Memory. Much faster than DRAM and does not require refreshing, but consumes more die area per bit. Used for on-chip cache (L1/L2/L3) in CPUs and GPUs rather than main system memory.
NAND flash that stores 3 bits per cell. The dominant NAND technology for both consumer and enterprise SSDs. Offers a good balance of cost, density, and endurance. 3D TLC is the standard for high-volume SSD production from Kioxia, Samsung, SK Hynix, and Micron.
A vertical electrical connection drilled through a silicon die, used to connect stacked dies in 3D packaging. TSV technology is what enables HBM to stack DRAM dies vertically and achieve its high bandwidth and density.
A high-performance mobile storage standard that uses a serial interface to deliver significantly faster read/write speeds than eMMC. UFS 3.1 is common in mid-to-high-end smartphones; UFS 4.0 is the current standard for flagship devices (Snapdragon 8 Gen 3+).
Memory dedicated to a GPU for storing frame buffers, textures, and intermediate compute data. In consumer graphics cards, VRAM is typically GDDR6 or GDDR6X. In data center AI accelerators, VRAM is implemented as HBM for much higher bandwidth.